Research graph
References from A buffer placement algorithm to overcome short-circuit power dissipation in mesh based clock distribution network. Local targets link to admitted publications; unresolved targets remain external evidence.
Meshworks: a comprehensive framework for optimized clock mesh network synthesis
10.1109/tcad.2010.2061130 · 2010 · External reference
High-performance clock mesh optimization
10.1145/2209291.2209306 · 2012 · External reference
Capacitance driven clock mesh synthesis to minimize skew and power dissipation
10.1587/elex.10.20130850 · 2013 · External reference
ISPD 2010 high performance clock network synthesis contest: benchmark suite and results
2010 · External reference
Unresolved reference
2003 · External reference
A sliding window scheme for accurate clock mesh analysis
2005 · External reference
Varius: a model of process variation and resulting timing errors for microarchitects
10.1109/tsm.2007.913186 · 2008 · External reference
Clock skew evaluation considering manufacturing variability in mesh-style clock distribution
10.1093/ietfec/e91-a.12.3481 · 2008 · External reference
Combinatorial algorithms for fast clock mesh optimization
10.1109/tvlsi.2008.2007737 · 2010 · External reference
Low power clock network design
10.3390/jlpea1010219 · 2011 · External reference
Unresolved reference
2008 · External reference
A novel scheme to reduce short-circuit power in mesh-based clock architectures
2008 · External reference
