Research graph
References from A calibration-free 12-bit 100-MS/s pipelined-SAR ADC with a gain-boosted residue amplifier using transient-current boosting in 65-nm CMOS. Local targets link to admitted publications; unresolved targets remain external evidence.
Successive approximation analog-to-digital converters: Improving power efficiency and conversion speed
10.1109/mssc.2016.2573978 · 2016 · External reference
Beyond sole parametric optimization design regimes: Understanding and advancing the frontiers of high-speed ADCs
10.1109/ojsscs.2026.3681529 · 2026 · External reference
A tale of two ADCs: Pipelined versus SAR
10.1109/mssc.2015.2442372 · 2015 · External reference
A SAR-assisted two-stage pipeline ADC
10.1109/jssc.2011.2108133 · 2011 · External reference
A 1.7 mW 11b 250 MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS
10.1109/jssc.2012.2217873 · 2012 · External reference
A 200MS/s, 77dB-DR two-stage SAR ADC with asynchronous pipelining and reference snubbers
2025 · External reference
A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration
10.1109/jssc.2011.2163556 · 2011 · External reference
A 13b 600-675MS/s tri-state pipelined-SAR ADC with inverter-based open-loop residue amplifier
10.1109/jssc.2022.3222162 · 2023 · External reference
A 65-dB-SNDR pipelined SAR ADC using PVT-robust capacitively degenerated dynamic amplifier
10.1109/jssc.2023.3235521 · 2023 · External reference
A 65.5-dB SNDR 100-MS/s pipelined-SAR ADC with nested negative-C and dynamic auto-zeroing residue amplifier achieving ≤ 2.2-dB ΔSNDR over −20°C to 125°C
10.1109/tcsi.2025.3637601 · 2026 · External reference
A bandwidth-adaptive pipelined SAR ADC with three-stage cascoded floating inverter amplifier
10.1109/jssc.2023.3268719 · 2023 · External reference
A 14b 500 MS/s single-channel pipelined-SAR ADC with reference ripple mitigation techniques and adaptively biased floating inverter amplifier
10.1109/jssc.2023.3290119 · 2023 · External reference
A 20-MS/s 13-bit pipelined SAR ADC with two-phase floating inverter amplifier
2025 · External reference
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC
10.1109/jssc.2015.2463094 · 2015 · External reference
A 12-bit 1.5-GS/s single-channel pipelined SAR ADC with a pipelined residue amplification stage
10.1109/jssc.2024.3412090 · 2025 · External reference
A pipelined-SAR ADC with a compensation-free two-stage amplifier
2025 · External reference
A 66.7dB-SNDR pipelined-SAR ADC with on-chip bit-weight calibration achieving ΔSNDR < 2.4 dB across PVT variations
2025 · External reference
A pipeline SAR ADC with second-order interstage gain error shaping
10.1109/jssc.2019.2962140 · 2020 · External reference
A calibration-free pipelined-SAR ADC with cross-stage gain-mismatch error shaping and inherent noise shaping
10.1109/jssc.2025.3624412 · 2025 · External reference
A 12-bit 200-MS/s pipelined SAR ADC with a closed-loop inverter-based residue amplifier and GRO-based time-domain quantization
2026 · External reference
A 12 b 180-MS/s pipelined-SAR ADC with a low-power calibration-free RA and hardware-efficient SAR logic
10.1109/lssc.2026.3697220 · 2026 · External reference
A 12-bit 1-GS/s SAR-assisted pipeline ADC with gain-stable dual-path residue amplification and partially look-ahead parallel conversion
2026 · External reference
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
10.1109/jssc.2010.2048498 · 2010 · External reference
A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure
10.1109/jssc.2010.2042254 · 2010 · External reference
A 13-bit 70-MS/s SAR-assisted cyclic ADC with charge-reused 2-bit/cycle operation
10.1109/tcsi.2026.3690163 · 2026 · External reference
A 12-bit 100-MS/s pipelined-SAR ADC with PVT-insensitive and gain-folding dynamic amplifier
10.1109/tcsi.2020.2982913 · 2020 · External reference
A 12-bit 40-MS/s pipelined SAR ADC for ultrasonic nondestructive testing applications
2026 · External reference
A 12-bit 78.8-dB SFDR 625-MS/s two-step pipelined-SAR ADC with self-adaptive common-mode capacitor multiplier
2026 · External reference
A 16-bit 2MSPS pipelined SAR ADC with digital background calibration in 0.18 μm CMOS
2026 · External reference
A 10-bit 50-MS/s SAR ADC with a monotonic capacitor switching procedure
10.1109/jssc.2010.2042254 · ExternalCitation · doi-reference
A 10-bit 100-MS/s reference-free SAR ADC in 90 nm CMOS
10.1109/jssc.2010.2048498 · ExternalCitation · doi-reference
A SAR-assisted two-stage pipeline ADC
10.1109/jssc.2011.2108133 · ExternalCitation · doi-reference
A 12-bit, 45-MS/s, 3-mW redundant successive-approximation-register analog-to-digital converter with digital calibration
10.1109/jssc.2011.2163556 · ExternalCitation · doi-reference
A 1.7 mW 11b 250 MS/s 2× interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS
10.1109/jssc.2012.2217873 · ExternalCitation · doi-reference
A 1 mW 71.5 dB SNDR 50 MS/s 13 bit fully differential ring amplifier based SAR-assisted pipeline ADC
10.1109/jssc.2015.2463094 · ExternalCitation · doi-reference
A pipeline SAR ADC with second-order interstage gain error shaping
10.1109/jssc.2019.2962140 · ExternalCitation · doi-reference
A 13b 600-675MS/s tri-state pipelined-SAR ADC with inverter-based open-loop residue amplifier
10.1109/jssc.2022.3222162 · ExternalCitation · doi-reference
A 65-dB-SNDR pipelined SAR ADC using PVT-robust capacitively degenerated dynamic amplifier
10.1109/jssc.2023.3235521 · ExternalCitation · doi-reference
A bandwidth-adaptive pipelined SAR ADC with three-stage cascoded floating inverter amplifier
10.1109/jssc.2023.3268719 · ExternalCitation · doi-reference
A 14b 500 MS/s single-channel pipelined-SAR ADC with reference ripple mitigation techniques and adaptively biased floating inverter amplifier
10.1109/jssc.2023.3290119 · ExternalCitation · doi-reference
A 12-bit 1.5-GS/s single-channel pipelined SAR ADC with a pipelined residue amplification stage
10.1109/jssc.2024.3412090 · ExternalCitation · doi-reference
A calibration-free pipelined-SAR ADC with cross-stage gain-mismatch error shaping and inherent noise shaping
10.1109/jssc.2025.3624412 · ExternalCitation · doi-reference
A 12 b 180-MS/s pipelined-SAR ADC with a low-power calibration-free RA and hardware-efficient SAR logic
10.1109/lssc.2026.3697220 · ExternalCitation · doi-reference
A tale of two ADCs: Pipelined versus SAR
10.1109/mssc.2015.2442372 · ExternalCitation · doi-reference
Successive approximation analog-to-digital converters: Improving power efficiency and conversion speed
10.1109/mssc.2016.2573978 · ExternalCitation · doi-reference
Beyond sole parametric optimization design regimes: Understanding and advancing the frontiers of high-speed ADCs
10.1109/ojsscs.2026.3681529 · ExternalCitation · doi-reference
A 12-bit 100-MS/s pipelined-SAR ADC with PVT-insensitive and gain-folding dynamic amplifier
10.1109/tcsi.2020.2982913 · ExternalCitation · doi-reference
A 65.5-dB SNDR 100-MS/s pipelined-SAR ADC with nested negative-C and dynamic auto-zeroing residue amplifier achieving ≤ 2.2-dB ΔSNDR over −20°C to 125°C
10.1109/tcsi.2025.3637601 · ExternalCitation · doi-reference
A 13-bit 70-MS/s SAR-assisted cyclic ADC with charge-reused 2-bit/cycle operation
10.1109/tcsi.2026.3690163 · ExternalCitation · doi-reference
