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References from Design and Characterization of a 10 Gb/s Clock and Data Recovery Circuit Implemented with Phase-Locked Loop. Local targets link to admitted publications; unresolved targets remain external evidence.
10.1109/mwsym.1994.335164
10.1109/mwsym.1994.335164 · External reference
10.1049/el:19940518
10.1049/el:19940518 · External reference
10.1109/mwsym.1995.406232
10.1109/mwsym.1995.406232 · External reference
10.1109/jssc.1979.1051309
10.1109/jssc.1979.1051309 · External reference
10.1109/4.90084
10.1109/4.90084 · External reference
10.1109/mwsym.1990.99625
10.1109/mwsym.1990.99625 · External reference
10.1049/el:19970140
10.1049/el:19970140 · External reference
