A novel MLP network implementation in CMOL technology

Hybrid CMOS/nanodevice technology is a well-known candidate to extend the exponential Moor-Law progress of microelectronics beyond the 10-nm frontier. This paper presents and evaluates a novel method for synaptic weights implementation of artificial neural networks in CMOL technology, a hybrid CMOS/nanodevice technology. In this novel method, the analog property of the I–V characteristic of the nanodevice is utilized to implement each neuromorphic synaptic weight. Each synaptic weight is also implemented by using one nanodevice instead of several nanodevices. Moreover, the proposed method is applied to the multilayer perceptron (MLP) network in CMOL technology. Our analysis shows that the power consumption and speed are effectively improved in the proposed method compared to other methods at the expense of a reasonable overhead defect tolerance.