Abstract
CdS/CdTe solar cells with a glass/FTO/CdS/CdTe/Au configuration often suffer from pinhole defects arising from incomplete grain coalescence and surface irregularities during thin-film deposition. These defects create leakage pathways that can lead to shunting after back contact deposition, thereby limiting device efficiency. In this work, thickness-dependent polyaniline (PANI) thin films were investigated for defect passivation and interface engineering. PANI films were deposited via anodic and cathodic electrodeposition, producing distinct structural, optical and electronic properties. Exploratory experiments evaluating PANI as a front buffer layer revealed severe thermal instability during high-temperature CdS/CdTe processing (400–420 °C), rendering it unviable for front-interface insertion. Conversely, incorporating PANI at the back contact as a pinhole-plugging layer effectively suppressed shunting currents through the formation of a metal–insulator–semiconductor (MIS) structure. The influence of back-contact PANI thickness was systematically investigated. Device performance improved significantly with an optimized PANI(A) deposition time of 4 min (corresponding to a nominal thickness of ~30 nm), increasing overall efficiency from 2.47 ± 0.10% to 4.23 ± 0.11%. Thinner layers provided insufficient pinhole coverage, while thicker films (≥162 nm) introduced excessive series resistance that degraded photocurrent collection. These findings demonstrate that while PANI is limited by high-temperature processing as a front buffer layer, thickness-controlled electrodeposited PANI serves as an effective back-contact pinhole-plugging interlayer to mitigate shunting and enhance CdS/CdTe solar cell efficiency.