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Privacy-aware community infrastructureK. Ike, K. Hirose, H. Yasuura
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A functional MOS transistor featuring gate-level weighted-sum and threshold operations
10.1109/16.137325 · 1992
Neuron-MOS binary-logic circuits featuring dramatic reduction in transistor count and interconnections
1993
10.1109/apcas.1996.569320
10.1109/apcas.1996.569320
Neuron MOS binary-logic integrated circuits—Part II: Simplifying techniques of circuit configuration and their practical applications
10.1109/16.210207 · 1993
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The generation of minimal threshold nets by an integer program
10.1109/pgec.1964.263921 · 1964
Implementation of threshold nets by integer linear programming
10.1109/pgec.1965.264120 · 1965
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