Abstract
Abstract
Wafer map pattern classification is an important component of semiconductor manufacturing inspection, but the severe class imbalance in datasets such as WM811K can cause conventional flat classifiers to be dominated by the abundant “None” samples, thereby weakening the recognition of minority defect patterns. To address this issue, this study proposes a dual-task collaborative learning framework that decomposes conventional nine-class classification into binary defect detection and eight-class defect recognition. A shared convolutional backbone is combined with Multi-Scale Context-Aware Attention (MSC-Attention) to enhance multi-scale defect representation and a Task-Gated Bottleneck (TGB) to perform task-specific feature routing. During joint training, “None” samples participate in the binary detection task but are excluded from the fine-grained classification loss through task masking, while dynamic loss weighting is employed to balance the optimization of the two tasks. During inference, a hierarchical coarse-to-fine strategy first distinguishes normal and defective wafer maps and activates fine-grained defect recognition only when a defect is detected. Experiments on WM811K demonstrate that the proposed framework achieves an ACC of 97.17% and a macro-F1 score of 84.97%, improving the macro-F1 score by 3.90 percentage points over the MultiCNN-based baseline. Among 20,556 defective test samples, 1,517 are classified as “None”, corresponding to a defect-pattern sensitivity of 92.62%. The complete TGB+MSC network contains only 0.963 M trainable parameters, indicating a favorable balance between classification performance and computational efficiency for automated wafer-map inspection.