Abstract
Focal-plane readout integrated circuits (ROICs) are key mixed-signal interface chips for infrared focal-plane arrays, and their bare-chip characterization is essential before detector hybridization. Conventional ROIC testing commonly relies on wafer probing, detector-coupled electro-optical platforms, or dedicated automated test equipment, which are costly and insufficiently flexible for single-die and small-array prototype verification. This paper presents an on-chip/off-chip co-designed test system for detector-free performance evaluation of a 32 x 32 hybrid graphene/colloidal-quantum-dot infrared ROIC. On chip, detector-equivalent test resources, test-control logic, and test-output paths are integrated to exercise the input bias setting, dark-current suppression, integrating conversion and other on-chip major functional modules and the overall operation of the target chip. Off chip, a reusable socket-based test board, low-noise power and reference generation circuits, a precision DAC module, and an FPGA/Zynq controller provide coordinated configuration, timing generation, data acquisition, and processing. Experimental results show that all 32 column readout circuits in the chip could be evaluated effectively by the test system. The measured maximum output swing of all columns exceeds the chip design specification of 2 V, with a minimum value of 2.4722 V and an average value of 2.5688 V, and the extracted output linearity is higher than 99.8%. The results demonstrate that the proposed system provides a low-cost, scalable, and automated solution for early-stage ROIC bare-chip verification before detector integration.