Abstract
This paper proposes a new Configurable Approximate Restoring Divider (CARD) to alleviate the tradeoff between accuracy and efficiency in unsigned array dividers. Configurable restoring subtractor cells (CRSCs), which can operate in both exact and approximate modes, are utilized as the fundamental building blocks in the design of CARD. These cells replace exact subtractor cells within the array structure, causing minimal effects on the output quotient bits when operating in approximate mode under the triangular replacement scheme. Various accuracy metrics and hardware characteristics have been evaluated for a 16-bit/8-bit unsigned configurable restoring divider. Synthesis results show that the proposed CARD uses 50% fewer resources, requires only 95 LUTs, achieves twice the speed, and consumes 40% less power compared to a conventional exact divider. The proposed CARD is coded in Verilog-HDL, implemented on the Artix-7 FPGA (XC7A35T-ICPG236C) board, and synthesized with Xilinx Vivado simulator. It demonstrates substantially higher accuracy while maintaining hardware characteristics similar to those of other reconfigurable designs. An image processing application is also presented to evaluate the functionality of the proposed CARD.