Abstract
Reducing neural-network precision does not necessarily reduce every FPGA resource, because synthesis can change how arithmetic is implemented. This study characterizes that interaction in sequential multilayer perceptrons on an Artix-7 XC7A35T using Vivado and Vitis HLS 2024.1. Optical-digits and Fashion-MNIST models are evaluated at 8-, 12-, and 16-bit weight and layer-output precision with three training seeds per workload. Under a common external interface, automatic mapping uses more routed look-up tables (LUTs) at 8 bits than at 12 bits for every seed on both workloads. An 18-configuration digits experiment changes only the first-layer multiply-accumulate mapping attribute while retaining the arithmetic, schedule, and package-pin fixture. Requesting DSP mapping at 8 bits reduces mean LUT usage from 286.33 to 210.33 (26.54%, or 0.37% of the device's LUTs) while increasing DSP usage from two to three (an increment of 1.11% of device DSP capacity). All mapping variants pass routed functional checks and 50 MHz static timing. Frozen held-out evaluation gives mean Fashion-MNIST accuracy of 86.78%, 87.18%, and 87.17% at 8, 12, and 16 bits. Two physical runs of an 8-bit digits design each verify 3,920 output codes over 392 inputs and report a 3,114-cycle start-to-done interval. The results establish a device-and flow-specific LUT/DSP tradeoff and show why precision comparisons should report realized primitives alongside accuracy, rather than treating bit width as a monotonic proxy for hardware cost.