A Hardware Input-Capture-Based Carrier Synchronization Method for Cascaded H-Bridge CPS-SPWM via Single-Fiber Multiplexing

In cascaded H-bridge (CHB) high-voltage drives using unipolar frequency-doubling carrier phase-shifted sinusoidal pulse width modulation (CPS-SPWM), unequal carrier phase offsets weaken switching-harmonic cancelation. This paper proposes a carrier-synchronization method that improves timing accuracy without adding dedicated synchronization fibers. The start edge of the downlink data frame is multiplexed as the common timing reference, hardware timer input capture removes interrupt-response latency from edge acquisition, and a dual-stage strategy combines standstill hard alignment with rate-limited on-line soft alignment. A phasor model links synchronization error to residual carrier-group amplitude and establishes a conservative accuracy target below 5 μs. On a complete 36-cell prototype, the measured spatial root-mean-square phase-offset deviation across the 11 Phase-A cell pairs referenced to A1 is 0.22° (1.22 μs), and the maximum absolute inter-cell phase-offset deviation is 0.36° (2.00 μs). A 380 V cascaded-output test confirms the expected 12 kHz dominant ripple and strong suppression of the 500 Hz and 1 kHz sidebands. Compared with a dedicated synchronization-link architecture, the proposed scheme halves the fiber and transceiver counts, requires only three pin-to-pin connections per-cell controller, and preserves address-free unified firmware. The method therefore provides a practical accuracy-cost compromise for large CHB systems, while full-voltage electromagnetic-compatibility validation remains future work.