Enhanced ONOFIC-Controlled Nano-Domino Logic Using FinFET and CNTFET Devices for Ultra-Low Leakage with AI-Assisted Optimization in 32 nm VLSI System

This paper presents an enhanced ONOFIC (ON/OFF Isolation Control) nano-domino logic framework implemented using 32 nm FinFET and CNTFET technologies for ultra-low leakage VLSI systems. The proposed ONOFIC technique employs feedback-controlled transistors to dynamically isolate leakage paths in the pull-up and pull-down networks, significantly reducing subthreshold leakage while preserving the high-speed characteristics of domino logic. Four ONOFIC-based architectures—Pull-Down, Dual-ONOFIC, Pull-Up, and Sandwiched ONOFIC—are designed and evaluated to investigate the trade-offs between leakage reduction, delay, and power consumption. In addition, an AI-assisted optimization approach is explored to automatically tune circuit parameters such as feedback bias and device sizing for improved leakage control and energy efficiency. HSPICE simulations using realistic FinFET and CNTFET models demonstrate up to 78% leakage reduction, approximately 45% total power savings, and 50–55% improvement in Power-Delay Product (PDP) compared with conventional domino logic techniques. The AI-optimized configurations further enhance leakage suppression and robustness under process-voltage-temperature (PVT) variations. These results confirm that combining ONOFIC-based leakage control with AI-assisted optimization provides an effective methodology for designing energy-efficient nano-scale VLSI systems suitable for modern low-power applications.