Abstract
In the semiconductor manufacturing industry, package chip-out is a common defect frequently encountered in trim and form (T/F) process. For thin shrink small outline package (TSSOP), top defect incurred during assembly manufacturing was the package chip-out located at the top surface of the package. In this scenario, the end-of-line (EOL) process parts per million (PPM) and its non-conformance report (NCR) are high. This paper discussed how the TSSOP20 package (hereinafter referred to as Device A) chip-out was addressed and replicated or simulated through package design simulation.