Self-Aligned AlO <i>x</i> Spacer Enabling 10 nm-Scaled InZnSnO Thin-Film Transistors for 2T0C DRAM

Abstract Oxide semiconductors are promising for low-power dynamic random access memory (DRAM) due to their ultralow off-state leakage and back-end-of-line compatibility. Continued transistor scaling is essential to further enhance electrical performances, however, conventional lithography faces significant challenges in defining 10 nm channels. In this work, we demonstrate InZnSnO thin-film transistors (IZTO TFTs) with an ultrashort channel length of 10 nm, defined by self-oxidized AlOx sidewall spacer via lithography-independent self-aligned approach. By systematically investigating the effects of indium composition and channel thickness on short-channel immunity, a 6 nm-thick low-indium IZTO channel delivers a maximum drain current of 540 μA μm–1 and an on/off current ratio of ∼ 108. Moreover, a 2T0C DRAM is constructed based on the high-performance short-channel IZTO TFTs, exhibiting a data retention time of ∼ 80 s at room temperature. The self-oxidized spacer technique offers a practical and scalable route toward high-density oxide-based memory technologies.